The present invention relates to a circuit for serializing a multi-bit data signal from a parallel format to a serial format, or for deserializing the multi-bit data signal from a serial format to a parallel format.
Deserializer circuits are known in which serial data bits are shifted from one stage to the next in a multi-stage shift register as the data bits are read, the number of shifts counted by a counter circuit until a desired number of bits in a frame of data have been read. When the entire frame of data is in the shift register, the bits are then written from the stages of the shift register in a parallel format. When the last bit of the frame is read into such a circuit, all of the bits must be shifted from one stage to the next, the counter must determine that this is the last bit, and all of the bits must be written out in a parallel format, all before the first bit of the next frame may be read into the shift register.
U.S. Pat. No. 4,015,252, issued Mar. 29, 1977 to Symanski for "High Speed Serial Data Synchronization Scheme" discloses a serial-to-parallel circuit having a plurality of active logic elements forming multiple delay lines. Data bits of serial data are transmitted down the delay lines until all of the data bits are at their respective delay line outputs. The data bits are then clocked into flip-flops as a parallel data word.
In an article by R. A. Schaadt titled "Shift Register Data Deserialization Without a Counter," IBM Technical Disclosure Bulletin, Vol. 23, No. 2, July 1980, a circuit is disclosed in which serial data bits of a byte of data and a marker are shifted through the stages of a shift register to determine when deserialization is complete. When the marker reaches the end of the shift register, the data bits are written out in a parallel format and all of the stages except the first are reset, with the set condition of the first stage acting as the marker for the next byte of data.
U.S. Pat. No. 4,377,806 issued Mar. 22, 1983 to Elliott et al for "Parallel to Serial Converter" discloses a converter for use in recording channel applications. The converter includes multiple channel input terminals adapted to receive parallel coded symbol inputs. Each bit received by an input is delayed incrementally by a predetermined amount depending upon the input line upon which it is received.
U.S. Pat. No. 4,429,300 issued Jan. 31, 1984 to Yamasawa et al for "High Speed Shift Register Circuit" discloses a shift register usable with a parallel to serial converter or a serial to parallel converter in which data bits are shifted through the shift register. Each bit of the shift register is set so as to become a predetermined logic condition. A detecting device detects whether or not the shift register has carried out the shift operations a predetermined number of times on the basis of the logical conditions of the bits in the shift register.
U.S. Pat. No. 4,680,733 issued July 14, 1987 to Duforestel et al for "Device for Serializing/Deserializing Bit Configurations of Variable Length" discloses circuitry for loading or reading bit configurations into or out of strings of latches formed in a ring under the control of a service processor.